In electronic equipment provided with a plurality of clocks, provision is sometimes made to use some of these clocks in succession on the same component, e.g. for the purpose of reducing energy consumption or for synchronizing its operation with the operation of other components. It is therefore necessary to use a clock signal multiplexing circuit whose output signal satisfies the usual specifications for clock signals, and in particular a minimum duration for each high level and for each low level.
Multiplexers of the conventional type in which the output signal is switched from a first input signal to a second input signal as soon as the selection signal specifies a changeover cannot satisfy this condition. The switching may take place after a shorter period than that specified since the previous level change in the first input signal. It may also take place at a shorter period than that specified before a level change in the second input signal.
It is now known from the patent U.S. Pat. No. 4,899,351 and from the patent application EP 0 254 406 to provide means for ensuring that the output signal satisfies these constraints on minimum duration. However, the switchover from a first input signal to a second input signal takes place only after a relatively long delay. Further, given the way the circuits described in the above-mentioned documents are controlled, they are ill-suited to cases where the number of input signals is greater than two.
An object of the present invention is thus to provide a clock signal multiplexing circuit in which the switching time between the switching request conveyed by the selection signal and the effective switchover to the second input signal depends solely on the frequencies of the first and second input signals, and is minimal given the above duration constraints.
The invention is applicable regardless of the number of clocks; moreover, the clocks need have no a priori phase or frequency relationship with each other or with the selection signal.